1. Field of the Invention
This invention relates to a method of fabricating a light emitting device and thus-fabricated light emitting device.
2. Description of the Related Art
Related arts are disclosed in:
(Patent Document 1) Japanese Laid-Open Patent Publication No. 2003-218383;
(Patent Document 2) Japanese Laid-Open Patent Publication No. 2003-209283;
(Patent Document 3) Japanese Laid-Open Patent Publication No. H8-115893; and
(Patent Document 4) Japanese Laid-Open Patent Publication No. 2005-317664.
Light emitting device having a light emitting layer section typically composed of an (AlxGa1-x)yIn1-yP alloy (where, 0≦x≦1, 0≦y≦1; referred to as AlGaInP alloy, or more simply AlGaInP, hereinafter) is fabricated by allowing the light emitting layer section to epitaxially grow on a GaAs single crystal substrate. The GaAs single crystal substrate is directly put into use as a device substrate portion. On the other hand, there is another practice of removing the GaAs substrate, which is a light-absorbing substrate (or opaque substrate), by grinding, etching or the like after the light emitting layer section was grown thereon, and instead forming a transparent GaP single crystal layer by bonding or vapor phase growth (any substrate fabricated by any method will be referred to as “GaP single crystal substrate” in a broad sense in this patent specification).
By the way, the device substrate portion composed of a III-V compound semiconductor such as GaAs and GaP has a cleavage plane along the {110} surface, so that it has been supposed that, if the side faces of chips produced by dicing agree with the {110} surface (where, deviation within the range from 1° to 25°, both ends inclusive, away from the exact {110} surface is allowable, given that the device substrate is an off-axis substrate), individualization into chips can be more simplified, by combining half-dicing of the wafer and breaking based on cleavage. Even for the case of adopting full-cut dicing of the wafer in order to produce the chips, the dicing surface agreed with the cleavage plane can reduce load of dicing, and can make chipping less likely to occur. Aiming at full exhibition of the above-described advantages, it has been a fixed idea for III-V compound semiconductor devices having the zincblende crystal structure, but not limited to the light emitting device within a scope of this invention, to align the direction of dicing with the <110> direction when they are manufactured by dicing wafers having the (100) main surface (also simply referred to as (100) wafer, hereinafter). For example, Patent Document 3 discloses a method of fabricating a light emitting device, involving dicing of a (100) wafer parallel to the orientation flat, wherein the orientation flat of the (100) wafer is generally formed parallel to the {110} surface, so that the dicing direction described in Patent Document 3 lies in the <110> direction.
However, investigations by the present inventors made clear that a device chip having the {110} surface on the side faces 100'S thereof, as shown in FIG. 10, tends to have a large number of crystal defects formed therein in parallel with the side faces of the constituent layers, because the crystal defects such as dislocation, ascribable to mechanical processing, tend to occur along the cleavage plane, and this may adversely affect fabrication of the device against expectation. More specifically, the dicing along the {110} surface composing the cleavage plane (that is, dicing carried out on the {100} surface composing the main surface of the wafer, in the direction targeted at the <110> direction) tends to produce a large crack CK by cleavage along the {111} surface, on the edge portion of the back surface of the device substrate portion (that is, on the opposite side of the light extraction surface having an electrode 9 formed thereon) which acts as a fixation surface during the dicing (the cleavage plane causing the crack is 35 to 36° away from the main surface of the device chip).
In order to solve this problem, the present inventors proposed to dice the wafer so as to make the {100} surface expose to the side faces 100'S as shown in FIG. 11, that is, to dice the wafer in the direction targeted at the <100> direction on the {100} surface composing the main surface of the wafer (Patent Document 4). In this case, the side faces of the device chip incline 45° away from the {110} surface composing the cleavage plane. Further detailed investigation by the present inventors, however, revealed that also this case similarly tends to produce a large crack CK as shown in FIG. 11 (the cleavage plane causing the crack inclined 45° away from the main surface of the device chip). This sort of crack is more likely to occur when a process step of obtaining the device chips by half-dicing of the wafer and succeeding breaking is adopted.
It is therefore a subject of this invention to provide a method of fabricating a light emitting device having an AlGaInP light emitting layer section, less likely to cause crack by cleavage on the edge portion of the back surface of the device chip, during dicing or breaking, and a light emitting device obtained by this method.